1. Field of the Invention
The present invention relates to a serial data receiver, and in particular to a serial data receiver that includes a mechanism to de-skew, i.e. center, the time position of the data bit capture window in an end-use environment.
2. Description of the Related Art
Disk and tape storage systems as well as communication networks typically pass data in serial fashion across a medium interface. FIG. 1 represents a conventional clock extraction method herein referred to as the sprocket concept of clock recovery. In this method, data 100 arrives asynchronously and without a separate clock signal for processing the data. Clock extraction circuitry, for example a phase-locked loop (PLL), recovers a continuous, periodic clock waveform 101 from discontinuous data 100. Recovered clock waveform 101 is represented as a gear having teeth and troughs 101A-101F. Troughs 101A, 101C, and 101F interdigitize with the logic one data bits 100A, 100B, and 100C, respectively. Troughs 10lB, 101D, and 101E correspond to the logic zeros on waveform 100.
The clock extraction circuitry serves to maintain the alignment (phase) of the troughs (windows) to the sprocket teeth (data pulses or logic ones), thereby extracting a continuous clock waveform with precise frequency and correct average phase alignment from the discontinuous and jittery serial data reference. Recovered clock waveform 101 is used to re-time the often jittery data pulses from which it was extracted to provide a time-stabilized, quantized (i.e. windowed), reconstructed data stream. The re-timed data and extracted clock are then provided to other circuitry downstream for processing such as deserialization or decoding.
A window is a repeating time cell defined by the period of the recovered clock and is used to standardize the time positions of incoming data bits. For example, FIG. 2 illustrates time line 200 along which data bits 201A-201F may occur within windows 202A-202F, respectively. The horizontal axis represents the time position of each pulse arrival and the vertical axis represents the probability of each pulse. The symmetry of windows 202A-202F is critical in minimizing bit errors. Specifically, if a window is truly symmetrical about the mean bit position, data bits 201A-201F are free to jitter within windows 202A-202F, respectively, by 50% of the window width in either direction while still being detected, i.e. received, properly. However, if the window position is skewed, i.e. asymmetrical, jittered bits which are displaced toward a boundary 203 of a window 202, for example, will more readily cross boundary 203 and fall into an adjacent detection window, thereby creating bit errors.
If the skew is systematic, i.e. highly repeatable from one data receiver to the next receiver, the skew can be eliminated by design. However, random variances between receivers leave undesirable, uncompensated skew. Under some circumstances, skew can be eliminated on a chip-by-chip basis by trimming. However, because trimming is performed in the integrated circuit manufacturing environment, and not in its end-use environment, some non-compensated skew effects remain.
FIG. 3 shows a serial data receiver 315 that includes a PLL 300 and a data latch 307. PLL 300 includes a phase detector 303, a low pass filter (LPF) 304, and a voltage controlled oscillator (VCO) 305. Phase detector 303 detects two input frequencies: one frequency provided to the positive input terminal of phase detector 303 by delay 301 (from raw data line 306) via line 301A and the other frequency provided to the negative input terminal of phase detector 303 by pulse gate 302 (from recovered clock line 313). Phase detector 303 generates an output phase-error signal that is determined by the phase difference between these two frequencies. The function of pulse gate 302 is to allow one feedback pulse from VCO 305 to be provided to the negative input terminal of phase detector 303 for each pulse on raw data line 306, and otherwise to block feedback pulses from VCO 305 in the absence of pulses on raw data line 306. This allows PLL 300 to maintain a block of its continuous signal on recovered clock line 313 to the discontinuous signals on its raw data line 306.
If the phase on raw data line 306 does not equal the phase on recovered clock line 313, the phase-error signal, after being filtered by LPF 304, causes the phase of VCO 305 to deviate in the direction of the phase on raw data line 306. If PLL 300 is properly designed, VCO 305 locks to the base clock frequency on raw data line 306 (the base clock frequency is the frequency the raw data would exhibit if every available bit position in the data stream had a pulse in it --ultimately equivalent to the frequency of the signal on recovered clock line 313) and ignores the missing pulses of the random data. PLL 300 is described in further detail in U.S. Pat. No. 5,172,397, which is herein incorporated by reference in its entirety.
The recovered clock is configured to have precise symmetry (i.e. 50% duty cycle), such that the average incoming data pulses on raw data line 306 fall exactly half-way in between predetermined (e.g. falling) clock edges on recovered clock line 313. Typically, this symmetry is achieved by operating VCO 305 at twice the desired clock frequency and employing it to clock a differential flip-flop in a toggle configuration,
PLL 300, using the above-described technique, subsequently referred to as clock symmetry-based windowing, minimizes skew in data windows for bit capture and transmittal by data latch 307. Fine de-skewing is achieved by feeding data latch 307 from a secondary delay line 301B, wherein the delay associated with 301B is nominally equal to that of the delay provided on line 301A, but can be shortened or lengthened as desired for window adjustment. This fine de-skewing is further described in U.S. Pat. No. 5,097,489, which is incorporated by reference in its entirety.
FIG. 4 shows serial data receiver 415 having a configuration similar to that of serial data receiver 315 (FIG. 3) except that raw data is fed directly to data latch 407 and the recovered clock signal on line 413, which is provided to flip-flops 409 and 410 of data latch 407, is not inverted (i.e. an inverter 311 of data latch 307 is eliminated (FIG. 3)). In this receiver configuration, delay 401 (instead of clock inversion) provides the necessary 180 degree phase shift between the raw data on line 406 and the recovered clock on line 413 to produce the data window. The magnitude of the delay associated with delay 401 is variable to allow for window adjustment for de-skewing purposes. This technique is referred to as delay line-based windowing.
FIG. 5 shows serial data receiver 515 also having a configuration similar to that of receiver 315 (FIG. 3) except phase detector 503 includes a pump 521 which provides a variable ratio of pump-up versus pump-down currents. Pump 521 produces a variable phase shift between the signals provided on its positive and negative input terminals. This shift is proportional to the up/down pumping current ratio. Thus, in this manner, the controlled phase shift adjusts, i.e. de-skews, the data window position. This technique is referred to as phase detector offset-based windowing.
However, serial data receivers 315, 415, and 515 all require significant window shifting to ascertain the position of the window edges as indicated by the bit error rate (BER). Specifically, to de-skew, the window is first shifted in one direction by the shifting means employed in that particular circuit until the BER crosses some pre-determined threshold. The same is done with a shift in the opposite direction. A mean position between the BER thresholds is then calculated and the window is shifted to that position.
This shifting method has numerous disadvantages:
1. The large amounts of window shifting required to reach the BER threshold entail associated circuit complexity, thereby increasing die area and power consumption.
2. The resolution of the window shift mechanism must be high through its entire shifting range since it is not known where the BER threshold will be encountered. Thus, once again, undesirable circuit complexity is required, thereby introducing an associated power penalty.
3. In some systems, such as in serial data receiver 515 (FIG. 5), pump 521 interferes with the equilibrium of PLL 500 since pump 521 skews the servo feedback mechanism of PLL 500 in order to move the data window. Thus, any bit detection errors, including those errors occurring during window de-skewing, simultaneously produce phase correction errors in PLL 500. These phase correction errors are undesirable, especially in demanding, low-margin (low SNR or high jitter) environments, such as disk storage systems.
Thus, a need exists for a simple, effective means to de-skew the data receiver window on a device-per-device basis while the serial data receiver is operating in its end-use environment.